In the fabrication of integrated circuits and other electronic devices, multiple layers of conducting, semiconducting and dielectric materials are deposited on or removed from a surface of a semiconductor wafer. Thin layers of conducting, semiconducting, and dielectric materials may be deposited by a number of deposition techniques. Common deposition techniques in modern processing include physical vapor deposition (PVD), also known as sputtering, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and electrochemical plating (ECP).
As layers of materials are sequentially deposited and removed, the uppermost surface of the wafer becomes non-planar. Because subsequent semiconductor processing (e.g., metallization) requires the wafer to have a flat surface, the wafer needs to be planarized. Planarization is useful in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize substrates, such as semiconductor wafers. In conventional CMP, a wafer is mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus. The carrier assembly provides a controllable pressure to the wafer, pressing it against the polishing pad. The pad is moved (e.g., rotated) relative to the wafer by an external driving force. Simultaneously therewith, a polishing composition (“slurry”) or other polishing solution is provided between the wafer and the polishing pad. Thus, the wafer surface is polished and made planar by the chemical and mechanical action of the pad surface and slurry.
Substrates in the electronics industry possess a high degree of integration where semiconductor bases include multilayers of interconnected structures. The layers and the structures include a wide variety of materials such as single crystal silicon, polycrystalline silicon, tetraethyl orthosilicate, silicon dioxide, silicon nitride, tungsten, titanium, titanium nitride and various other conductive, semiconductive and dielectric materials. Because these substrates require various processing steps, including CMP to form a final multilayered interconnected structure, it is often highly desirable to utilize polishing compositions and processes that are selective for specific materials depending on the intended applications. Unfortunately, such polishing compositions can cause excessive dishing of the conductive material which can lead to erosion of dielectric material. The topographical defects which can result from such dishing and erosion can further lead to non-uniform removal of additional materials from the substrate surface, such as barrier layer material disposed beneath the conductive material or dielectric material and produce a substrate surface having less than desirable quality which can negatively impact the performance of the integrated circuit.
Chemical mechanical polishing has become a preferred method for polishing tungsten during the formation of tungsten interconnects and contact plugs in integrated circuit designs. Tungsten is frequently used in integrated circuit designs for contact/via plugs. Typically, a contact or via hole is formed through a dielectric layer on a substrate to expose regions of an underlying component, for example, a first level metallization or interconnect. Unfortunately, many CMP slurries used to polish tungsten cause the problem of dishing. The severity of the dishing can vary but it typically is severe enough to cause erosion of underlying dielectric materials such as TEOS.
Another problem associated with polishing metals such as tungsten is corrosion. The corrosion of metals is a common side-effect of CMP. During the CMP process the metal polishing slurry that remains on the surface of the substrate continues to corrode the substrate beyond the effects of the CMP. Sometimes corrosion is desired; however, in most semiconductor processes corrosion is to be reduced or inhibited. Corrosion may also contribute to surface defects such as pitting and key-holing. These surface defects significantly affect the final properties of the semiconductor device and hamper its usefulness. Therefore, there is a need for a CMP polishing method and composition for tungsten which inhibits dishing of tungsten and erosion of underlying dielectric materials such as TEOS and also reduces corrosion rate.